The present invention relates to nonvolatile semiconductor memory devices, and in particular, to a nonvolatile semiconductor memory device capable of reducing a threshold value setting time of a reference cell.
Conventionally, as the flash memory used most generally, there is ETOX (EPROM Thin Oxide, which is a registered trademark of Intel). FIG. 13 shows a schematic sectional view of this ETOX type flash memory. In this memory, as shown in FIG. 13, a floating gate FG is formed between a source S and a drain D via a tunnel oxide film TF on a substrate, and a control gate CG is formed via an interlayer insulation film LF on this floating gate FG.
The principle of operation of the flash memory of this ETOX type will be described next. Table 1 provided below shows voltage conditions during write, erase and read operations. That is, during write, a voltage Vpp (9 V, for example) is applied to the control gate CG, the source S is made to have a reference voltage Vss (0 V, for example), and a voltage of 5 V is applied to the drain D. As a result, a large current flows through the channel layer, and hot electrons are generated in a portion of a high electric field on the drain side, so that electrons are injected into the floating gate FG, raising the threshold voltage. FIG. 14 shows this written state as a programmed state. In FIG. 14, the horizontal axis represents the threshold voltage, and the vertical axis represents the number N of memory cells.
TABLE 1Application voltage in each modeControlGateDrainSourceSubstrateWrite  9 V5 V/Open0 V0 VErase−9 VOpen6 V0 VRead  5 V1 V0 V0 V
During erase, a voltage Vnn (−9 V, for example) is applied to the control gate CG, and a voltage Vpe (6 V, for example) is applied to the source S to extract electrons from the floating gate FG on the source side, lowering the threshold voltage. The threshold voltage in this erased state is shown in FIG. 14.
During this erase, a BTBT (Band To Band Tunneling) current flows. If this BTBT current is generated, then hot holes and hot electrons are generated at the same time. Among these, the hot electrons flow toward the substrate, while the hot holes are pulled toward the tunnel oxide film TF side and trapped in the oxide film TF. It is generally said that this phenomenon causes degraded reliability.
In the read operation, a voltage of 1 V is applied to the drain D, and a voltage of 5 V is applied to the control gate CG. At this time, the threshold voltage is in the erased state, and current flows through the memory cell when the threshold voltage is low. In this case, the stored information of this memory cell is determined to be “1”. When the memory cell is in the programmed state and the threshold voltage is high, no current flows through the memory cell. In this case, the stored information of this memory cell is determined to be “0”.
A read method in this case will be described more in detail referring to the construction of the sense amplifier circuit shown in FIG. 11. Normally, as shown in FIG. 11, the flash memory read operation is executed by comparing a current Im that flows through the memory cell (main cell) of a main array with a current Ir that flows through a reference cell and determining whether the data retained in the main cell is either “0” or “1”.
In detail, it is determined that the above-mentioned data is “1” when Im>Ir, and it is determined that the data is “0” when Im<Ir. In order to thus make determination, the threshold value of the reference cell is required to be a value intermediate between the threshold value of the cell in the written state and the threshold value in the erased state. This intermediate value is, for example, 3.5 V.
The threshold value of this reference cell has conventionally been required to be an accurate value in consideration of reading speed, reliability and so on. For example, there is required an accuracy within 3.5 V±0.1 V. With regard to the word line voltage, both RWL and WL have same voltage (5 V, for example).
On the other hand, in the recent flash memories, reading speed is increased by high-speed access, a page-mode technique, a synchronous technique and so on. In particular, if the page mode technique and the synchronous technique are used, then the number of memory cells to be read through one-time read (sense) operation significantly increases. In this case, if it is attempted to achieve an increase in reading speed, then the state of the main cell and the state of the reference cell are required to be made as similar as possible during read. If it is attempted to satisfy this requirement, then the number of reference cells is to be disadvantageously increased.
For example, when the read operation is further increased in speed by using the page mode technique in the prior art, a sense system in the memory device has a construction as shown in FIG. 12. FIG. 12 shows a memory array in one block, which is constructed of 256 word lines WL0 through WL255 and 2048 bit lines BL0 through BL2032. Moreover, in the read operation, there is a construction in which 128 memory cells MS can be simultaneously read in one-time operation. On the other hand, in order to achieve high-speed read on the reference side, one reference cell RFC0 (,RFC1, . . . , RFC127) is arranged for one sense amplifier SA0 (,SA1, . . . , SA127).
Problems of the aforementioned conventional nonvolatile semiconductor memory device will be described next. FIG. 10 shows a circuit construction in which the threshold value of the reference cell of a reference cell array 103 is adjusted by programming (writing) the reference cell in the aforementioned memory device. The threshold value of the reference cell in this case is required to fall within the range of 3.5 V±0.1 V as described hereinabove. As a method for adjusting this threshold value, there is used a method for executing gradual programming by using an external controller and making the threshold value of one memory cell have a voltage of 3.5 V±0.1 V. This threshold value adjustment is executed during testing.
When the threshold value adjustment is executed, a command of the program operation of this reference cell is inputted from a program control circuit 101 to a sense amplifier array 105 and a reference cell word line voltage generator circuit 106. Then, one pulse of a program pulse is inputted from this sense amplifier array 105 and the reference cell word line voltage generator circuit 106 to the reference cell array 103. This program pulse is assumed to have, for example, a control gate voltage of 6 V, a drain voltage of 5 V and a pulse width of 1 μsec. Moreover, a gate voltage when this threshold value adjustment is executed is set at a value lower than that of normal program so as not to exceed the threshold value of the memory cell of the main array 102.
Next, a current, which flows directly from a pad PAD shown in FIG. 12 to the reference cell RFC0, is measured, and the threshold value is measured from the current. In this case, if it is determined that the threshold value is not higher than 3.4 V, then the program pulse is further applied to the reference cell RFC0. This threshold value adjustment operation is executed until the threshold value of the reference cell RFC0 comes to have a voltage of not lower than 3.4 V. The prior art of Japanese Patent Laid-Open Publication No. HEI 10-261768 also discloses a threshold value adjustment system like this.
If the threshold value adjustment of the reference cell RFC0 ends, then the threshold value adjustment of the reference cell RFC1 is executed. This threshold value adjustment operation is executed up to RFC127.
Next, a time required for the threshold value adjustment is examined. In the operation of adjusting the threshold value of one reference cell, the number of program pulses applied to one reference cell is normally required to be about 100 times. It is herein assumed that a time of 10 μsec is required for one program pulse apply operation (including setup operation and so on) and a time of 100 μsec is required for the threshold value read operation. Then, a time T required for the threshold value adjustment operation for one reference cell becomes about 11 msec as calculated by the following equation (101).T=(100+10) μsec×100=11 (msec)  (101)
Moreover, since there are 128 reference cells (RFC0 through RFC127), a total time TT required for the threshold value adjustment operation of these 128 reference cells RFC0 through RFC127 becomes about 1.4 sec as calculated by the following equation (102).TT=11 msec×128=1.4 (sec)  (102)
As described above, the time required for the threshold value adjustment of the reference cell (the time being also referred to as a testing time) becomes very long according to the aforementioned prior art.
Then, as described hereinabove, if the number of memory cells to be read through one-time read (sense) operation is significantly increased by the page mode technique and the synchronous technique, then the number of reference cells is also increased in accordance with this, disadvantageously increasing the threshold value adjustment time.